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Chapter 3: Hardware Description
R
Table 3-18:
ML555 Board Clock Sources (Continued)
Clock Designator
PCIE_REFCLKN
Output
Differential
(system board
Type
LVDS (6)
Frequency
100 MHz
Spread
Destination Pin
FPGA U10 GTP_DUAL tile X0Y2 MGTREFCLK_N
pin Y3 and FPGA U10 global clock input pin J17
input)
Spectrum
Notes:
1. Differential clock inputs to the FPGA should use the IBUFDS input buffer library primitive. Setting the DIFF_TERM attribute of the
IBUFDS to "TRUE" provides 100 Ω on-chip termination for the LVDS clock source driver.
2. The clock synthesizer has a voltage controller oscillator (VCO) that operates in the 250 to 700 MHz range. The VCO output can be
divided by 1, 2, 4, or 8 to obtain various clock frequencies.
3. Input reference clock frequency for Clock Synthesizer 1 is 10 MHz. The minimum clock adjustment granularity is 10/8 or 1.25 MHz
steps.
4. Input reference clock frequency for Clock Synthesizer 2 is 25 MHz. The minimum clock adjustment granularity is 25/8 or 3.125 MHz
steps.
5. When SMA connectors J12 and J13 are used to provide a source clock to GTP_DUAL tile X0Y3 MGTREFCLK, in-line DC blocking
capacitors should be placed between the test equipment outputs and SMA clock inputs. AC coupling is recommended for GTP clock
inputs. All GTP clock inputs, with the exception of the SMA clock inputs, are AC coupled on the ML555 board assembly.
6. The ML555 board layout provides two methods of interfacing the PCIE_REFCLK to the FPGA. The default method is to AC couple
the 100 MHz PCIE_REFCLK directly to the GTP_DUAL tile X0Y2 MGTREFCLK input pins. An alternative method is to remove two
0 Ω resistors and install an ICS874003-02 PCI Express Jitter attenuator module, which provides a 100, 125, or 250 MHz reference clock
to the GTP transceiver. The jitter attentuator has two LVDS outputs that connect to the GTP and FPGA global clock inputs. One of
the jitter attentuator LVDS outputs is connected to the MGTREFCLK inputs of GTP_DUAL tile X0Y2 for PCI Express lanes 0 and 1.
The PCIE_REFCLK is also connected to the FPGA global clock network on pins J16 and J17. Internal FPGA clock buffers distribute
this clock to other GTP_DUAL tiles for PCI Express operation. The architecture of the FPGA permits an external MGTREFCLK to be
driven a maximum of three GTP_DUAL tiles up or down. See “Serial Bus Clocking with Optional ICS874003-02 Clock Jitter
Attenuator (PCI Express Operation),” page 60 for additional information.
54
www.xilinx.com
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
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